記憶體層級平行

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記憶體層級平行英语Memory-level parallelism,縮寫為 MLP,又譯為內存級並行),平行計算技術的一種,是電腦架構的一種,能夠同時進行數個記憶體操作,特別是在快取未命中(cache miss),或轉譯後備緩衝區未命中(TLB miss)時。

在單核心處理器架構下,記憶體層級平行可以被視為是一種特殊的指令層級平行(IPL)。它也經常在超純量架構下出現。

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參考文獻[编辑]

  • "Enhancing memory level parallelism via recovery-free value prediction." H. Zhou and T. M. Conte. Proceedings of the 17th Annual International Conference on Supercomputing, ICS 2003.
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  • "Coming challenges in microarchitecture and architecture", Ronen, R.; Mendelson, A.; Lai, K.; Shih-Lien Lu; Pollack, F.; Shen, J.P. Proceedings of the IEEE Volume: 89 Issue: 3 Mar 2001
  • "MLP yes! ILP no!" (abstract / slides), A. Glew. In Wild and Crazy Ideas Session, 8th International Conference on Architectural Support for Programming Languages and Operating Systems, October 1998.