User:Danny.umd/My-Duck-2

XDR DRAM is a high performance RAM interface. It is based on Rambus RDRAM, and competes with Synchronous and Double-Data-Rate (DDR) DRAM. XDR was designed to be effective in small, high-bandwidth consumer systems, high-performance memory applications, and high-end GPUs. It eliminates the unusually high latency problems that plagued early forms of RDRAM. Rambus owns the rights to the technology. XDR will be used by Sony in the upcoming PlayStation 3 console.[1]

參數

性能

• 初始的時脈頻率為400MHz、600MHz、800MHz以及1GHz。
• Octal Data Rate (ODR): Eight bits per clock per lane provides 3.2 Gbit/s at 400MHz.
• Each chip provides eight or 16 lanes, providing 25.6 or 51.2 Gbit/s (or 3.2 to 6.4 GB/s) at 400MHz.

特點

• Bi-directional differential Rambus Signalling Levels (DRSL)
  • This uses differential open-collector driver, voltage swing 0.2V. It is not the same as LVDS.[2]
• Programmable on-chip termination
• Adaptive impedance matching
• Eight bank memory architecture
• Up to four bank-interleaved transactions at full bandwidth
• Point-to-point data interconnect
• CSP packaging
• Dynamic request scheduling
• Early-read-after-write support for maximum efficiency
• Zero overhead refresh

用電需求

• 1.8 V Vdd
• Programmable ultra-low-voltage DRSL 200 mV swing
• Low-power PLL/DLL design
• Power-down self-refresh support
• Dynamic data width support with dynamic clock gating
• Per-pin I/O power-down
• Sub-page activation support

Ease of system design

• Per-bit FlexPhase circuits compensate to a 2.5 ps resolution
• XDR Interconnect uses minimum pin count

Low latency

• 1.25/2.0/2.5/3.33 ns request packets

See also

• RDRAM
• XDR2 DRAM

External links

• Rambus XDR Product Page
• Rambus FlexIO CPU Interface provides XDR Interface
• "XDR2 to quintuple memory data transfer speeds by 2007" by Scott Fulton