底數經濟度
外觀
底數經濟度是一種將某數作為進位制的底數時,該進位制表達數的效率,其定義為數在某進位制下表達的位數與底數或該計數系統中每個位數可能的符號之數量的乘積。為量化不同底數的進制或計數系統在表示一個數時的效率的一種方法,尤其用於計算機系統,評估特定計數系統的儲存效率。
底數經濟度的概念亦用於組織結構、網路等領域。
定義
[編輯]對一數N在特定的底數b下,底數經濟度 定義為:
其中,表示下取整函數;表示以為底的對數。
若b和N皆為正整數,則底數經濟度值與在以為底的進制下的位數與的乘積[1]。
底數經濟度列表
[編輯]底數 b N = 1 to 6 E(b,N)平均
N = 1 to 43 E(b,N)平均
N = 1 to 182 E(b,N)平均
N = 1 to 5329 E(b,N)平均
E (b )/E (e )的
相對大小1 3.5 22.0 91.5 2,665.0 — 2 4.7 9.3 13.3 22.9 1.0615 e 4.5 9.0 12.9 22.1 1.0000 3 5.0 9.5 13.1 22.2 1.0046 4 6.0 10.3 14.2 23.9 1.0615 5 6.7 11.7 15.8 26.3 1.1429 6 7.0 12.4 16.7 28.3 1.2319 7 7.0 13.0 18.9 31.3 1.3234 8 8.0 14.7 20.9 33.0 1.4153 9 9.0 16.3 22.6 34.6 1.5069 10 10.0 17.9 24.1 37.9 1.5977 12 12.0 20.9 25.8 43.8 1.7765 15 15.0 25.1 28.8 49.8 2.0377 16 16.0 26.4 30.7 50.9 2.1230 20 20.0 31.2 37.9 58.4 2.4560 30 30.0 39.8 55.2 84.8 3.2449 40 40.0 43.7 71.4 107.7 3.9891 60 60.0 60.0 100.5 138.8 5.3910
參考文獻
[編輯]- ^ Brian Hayes. Third Base. American Scientist. 2001, 89 (6): 490 [2013-07-28]. doi:10.1511/2001.40.3268. (原始內容存檔於2014-01-11).
延伸閱讀
[編輯]- S.L. Hurst, "Multiple-Valued Logic-Its Status and its Future", IEEE trans. computers, Vol. C-33, No 12, pp. 1160–1179, DEC 1984.
- J. T. Butler, "Multiple-Valued Logic in VLSI Design, 」 IEEE Computer Society Press Technology Series, 1991.
- C.M. Allen, D.D. Givone 「The Allen-Givone Implementation Oriented Algebra", in Computer Science and Multiple-Valued Logic: Theory and Applications, D.C. Rine, second edition, D.C. Rine, ed., The Elsevier North-Holland, New York, N.Y., 1984. pp. 268–288.
- G. Abraham, "Multiple-Valued Negative Resistance Integrated Circuits", in Computer Science and Multiple-Valued Logic: Theory and Applications, D.C. Rine, second edition, D.C. Rine, ed., The Elsevier North-Holland, New York, N.Y., 1984. pp. 394–446.