# 加法器

A B C S
0 0 0 0
1 0 0 1
0 1 0 1
1 1 1 0

## 全加器

A B Cin Cout S
0 0 0 0 0
1 0 0 0 1
0 1 0 0 1
1 1 0 1 0
0 0 1 0 1
1 0 1 1 0
0 1 1 1 0
1 1 1 1 1

$T_{FA} = 2 \cdot T_{XOR} = 2 \cdot 3 D = 6 D$

$T_c = 2 D$

## 更复杂的加法器

### 漣波进位加法器

$T_{CRA}(n) = T_{HA} + (n-1) \cdot T_c + T_s = T_{FA} + (n-1) \cdot T_c = 6 D + (n-1) \cdot 2 D = (n+2) \cdot 2 D$

$T_{CRA_{[0:c_{out}]}} = T_{HA} + n \cdot T_c = 3 D + n \cdot 2 D$

$T_{CRA_{[c_0:c_n]}}(n) = n \cdot T_c = n \cdot 2 D$

### 超前进位加法器

• 生成（Generate）信号：$G_i = x_i \cdot y_i$
• 传输（Propagate）信号：$P_i = x_i \oplus y_i$

## 参考文献

1. ^ 1.0 1.1 1.2 Stephen Brown, Zvonko Vranesic. Fundamentals of Digital Logic with Verilog Design. McGraw-Hill Education. ISBN 0-07-283878-7.
2. ^ Geoffrey A. Lancaster. Excel HSC Software Design and Development. Pascal Press. 2004: 180. ISBN 9781741251753.
3. ^ M. Morris Mano. Digital Logic and Computer Design. Prentice-Hall. 1979: 119-123. ISBN 0-13-214510-3.
4. ^ 4.0 4.1 邓元庆，关宇，贾鹏，石会. 数字设计基础与应用. 清华大学出版社. ISBN 978-7-302-21406-9.
5. ^ Burgess, N. Fast Ripple-Carry Adders in Standard-Cell CMOS VLSI. 20th IEEE Symposium on Computer Arithmetic. 2011: 103–111.